View CXA1391Q_24029.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXA1391Q/R
Processing IC for Complementary Color Mosaic CCD Camera
Description The CXA1391Q/R is a bipolar IC developed for signal processing in complementary color mosaic CCD cameras. Features * Low power consumption (170mW) * Number of delay lines used for signal processing can be selected according to the system requirements * The LPF peripheral to 1H delay line is built in Structure Bipolar silicon monolithic IC Applications Complementary color mosaic CCD cameras Block Diagram and Pin Configuration (Top View)
DLCO OUT C1 GAIN DLC1 IN R MTX
48 47 46 45
CXA1391Q 64 pin QFP (Plastic)
CXA1391R 64 pin LQFP (Plastic)
690 mW (LQFP: Ta = 25C, without P.C.B) Recommended Operating Conditions * Supply voltage Vcc 4.75 to 5.25 V * Ambient temperature Topr -20 to +75 C
CLP C MPX2 CLP C B CLP C G B CONT R CONT B MTX B GAIN R GAIN CLF C R C LEVEL
Absolute Maximum Ratings * Supply voltage Vcc * Storage temperature Tstg * Allowable power dissipation PD
7 -55 to +150
V C
CLP C MPX1
ID
44
43
42
41
40
39
38
37
36
35
34
33
C0 S2 IN 49 S1 IN 50 CLP C YO 51 DLY0 OUT 52 DLY1 OUT 53 Y1 GAIN 54 DLY1 IN 55 DLY2 IN 56 Y2 GAIN 57 GND 2 58 LPF ADJ 1 59 GC GC LPF Y0
LPF
WB CONTROL C0 CLP -CB B LPF (CLP2) CR G & Y MATRIX R WB AMP C1 MPX LPF
32 C SLICE
LPF
CLP (CLP4)
GC
R-WB G-WB B-WB
CLP (CLP4)
CLP (CLP2)
31 WB DC 30 WB B
Y0
LPF
G-r
Y0 Y1
B-r
29 WB G 28 WB R
SLICE
R-r
27 C-r CONT 26 GND 1
CLP (CLP4) Y2
Y2 Y1
Y0
LPF
YL MTX
15 16
CLP (CLP4) Y1
LPF
R-r G-r B-r
r
25 YL OUT 24 CS OUT 23 CS GAIN
KNEE
KNEE
KNEE
CLP V-APCN (CLP4)
ABS
GC
CS VAP MAX LPF CS-Y CS
-
-
- 2H APCN
R-Y MTX R-Y B-Y Hue & GC
3H APCN
22 R - Y HUE 21 B - Y HUE 20 R - Y OUT 19 B - Y OUT 18 B - Y GAIN
V-APCN
LPF ADJ 2 60 LPF ADJ 3 61 VCC 62 Y-r CONT 63 YH IN 64 CLP (CLP2)
1 2
V-APCN LPF YH0
G ch SLICE SLICE CLP
CS-Y
CLP (CLP4)
YH1
CLP (CLP4)
GC
YH1
r
3
YH0
GC
B-Y
17 R - Y GAIN
4
5
6
7
8
9
10
11
12
13
14
DLYH OUT
VAP OUT
CLP C DLYH
DLYH GAIN
VAP GAIN
CLP C YH
DLYH IN
YH OUT 1
YH OUT 2
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
CLP C VAP
VAP SLICE
CLP C CS
CS IN
CLP4
CLP2
TP
E89Z18-ST
CXA1391Q/R
Pin Description PIn No. Symbol Pin voltage Equivalent circuit Description
1 2.4k 2.4k 800
1
CLP C YH
3 to 3.5V
1k
147
Capacitor connecting pin for YH clamp (Clamp at CLP2)
180A
80A
1k 147
2
DL YH IN
2
DL YH signal input pin (Input from 1H delay line)
5k 80A
3.65V Sig: Typ. 200mV (Positive polarity)
3 2.6k 2.6k 1k
3
CLP C DL YH
1k
147
2.6 to 3.8V
Capacitor connecting pin for DL YH clamp (Clamp at CLP4)
40A
180A
200
DL YH signal output pin (To 1H delay line)
4
4
DL YH OUT
2.7 to 3.1V
400A
Sig: Typ. 400mV Max. 600mV (Negative polarity)
Note) Pin voltage for input and output pins indicate black level. -2-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
100
YH1 signal output pin Sig: Typ. 1V Max. 1.5V (Positive polarity)
5
YH OUT1
1.9 to 2.3V
5 160A
100
YH2 signal output pin Sig: Typ. 1V Max. 1.5V (Positive polarity)
6
YH OUT2
1.9 to 2.3V
6 400A
2.6 to 3.0V (YH) 7 TP 2.5 to 2.9V (G)
500
7 80A
TP OUT (adjusting pin) 1H mode: Outputs YH1-YH0 0H mode: Outputs Gch C-slice OUT (Mode selection is executed through Pin 8)
0V (0H Mode) 8 DL YH GAIN 1.8 to 5V (1H Mode)
1k 100k
DL YH signal gain control pin (For 1H delay line gain compensation of YH) TP (Pin 7) mode selection 0H Mode: 0V 1H Mode: 1.8 to 5V DLY1 signal gain control pin (1H delay line gain compensation) 0V: DLY1 signal gain control is executed in common with DLY2 signal gain control. 1.8 to 5V: DLY1 signal gain control is executed independently from DLY2 signal gain control.
54
Y1 GAIN
0V: Common control by Pin 57 1.8 to 5V Independent control
30k
30k
147
100k
40A
8 54
-3-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
5V
9
CLP4
0
1k
30k
CLP4 pulse input pin (BLK clamp) (CMOS level input, VTH = 2.5V)
9 5V 10 40A
10
CLP2
0
CLP2 pulse input pin (OPB clamp) (CMOS level input, VTH = 2.5V)
431
V-APCN signal output pin 11 VAP OUT 2.6 to 3.0V
280A 11
Sig: Max. 1.2Vp-p
1k 147 12 25k 25k
12
VAP GAIN
1.8 to 5V (Control)
V-APCN signal output level adjustment pin
40A
2.6k
2.6k 1k
13
CLP C VAP
3.4 to 3.8V
147 147 180A 13 12A
Capacitor connecting pin for VAP clamp (Clamp at CLP4)
V-APCN: Vertical Aperture Compensation
-4-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
1k 147 14 30k 30k
14
VAP SLICE
1.8 to 5V (Control)
V-APCN signal dark slice volume adjustment pin
40A
2.6k
2.6k 1k
15
CLP C CS
3.5 to 3.7V
147 147 180A 15 20A
Capacitor connecting pin for CS clamp (Clamp at CLP4)
2.6k 147
2.6k
1k
16
CS IN
C-Couple input 2.9 to 3.3V
AGC CS signal input pin
16 147
Sig: Max. 1V
180A
20A
-5-
CXA1391Q/R
17
R-Y GAIN
0V: R-G output 1.8 to 5V: R-Y output 0V: B-G output 1.8 to 5V: B-Y output 1.8 to 5V (Control) 2.75 to 3.15V (Hue OFF) 2.35 to 2.75V (Hue ON)
R-Y signal output level adjustment pin Pin 20 Mode select 0V: R-G output 1.8 to 5V: R-Y output B-Y signal output level adjustment pin Pin 19 Mode select 0V: B-G output 1.8 to 5V: B-Y output V-APCN CS signal gain control pin
18
B-Y GAIN
23
CS GAIN
19 20
B-Y OUT R-Y OUT
46
DLC0 OUT
1.8 to 2.2V
52
DLY0 OUT
1.4 to 1.8V
53
DLY1 OUT
2.8 to 3.2V
21
B-Y Hue
0V:
B-Y hue control pin
R-Y hue control pin
-6-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
431
CS signal output pin 24 CS OUT 1.5 to 1.8V
24 200A
Sig: Max. 1V
431
25
YL OUT
1.9 to 2.3V
25 80A
YL signal output pin
26
GND1
GND
1k
100k
27
C- CONT
0V: Typ. curve
30k 30k 147
Chroma (R.G.B) curve adjustment pin
40A 27
-7-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description R signal output pin WB Mode: Sig: Typ. 400mV Mode: Sig: Typ. 500mV
28
28
WB R
1.4 to 2V
431
29
WB G
1.4 to 2V
200A
29 30
G signal output pin WB Mode: Sig: Typ. 400mV Mode: Sig: Typ. 500mV B signal output pin WB Mode: Sig: Typ. 400mV Mode: Sig: Typ. 500mV When used as output pin, it is an Auto WB DC output pin. Pin 28, 29 and 30 turn to WB mode. When connected to Vcc: Pins 28, 29 and 30 turn to mode.
30
WB B
1.4 to 2V
431
1k
31
WB DC
1.4 to 2V
200A 31
300
100k
100k
1k
32
32
C SLICE
0V: Slice OFF
18k
18k
Chroma (R.G.B) signals dark slice level adjustment pin
67A
33
C LEVEL
1.8 to 5V (Control)
33 47 30k
1k
Chroma (R.G.B) gain control pin (Chroma modulation factor control for all 3 channels)
30k
47
C1 GAIN
1.8 to 5V (Control)
40A
DL C1 signal gain control pin (1H delay line gain compensation)
-8-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description Capacitor connecting pin for R WB amplifier clamp (Clamp at CLP2)
1k
34
CLP C R
3.0 to 3.6V
2.2k 2.2k
1k
147
35
CLP C G
3.0 to 3.6V
Capacitor connecting pin for G WB amplifier clamp (Clamp at CLP2)
34 35 36 125A 40A
36
CLP C B
3.0 to 3.6V
Capacitor connecting pin for B WB amplifier clamp (Clamp at CLP2)
37
R GAIN
1.8 to 5V (Control)
147 37 40 15k
1k
Rch WB amplifier gain control pin (Pre-WB)
15k
40
B GAIN
1.8 to 5V (Control)
80A
Bch WB amplifier gain control pin (Pre-WB)
38
R CONT
2.5 to 4.6V
147 38 39
1k
Rch WB amplifier gain control pin
39
B CONT
2.5 to 4.6V
10A
Bch WB amplifier gain control pin
-9-
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
1k 147 5V 0
30k
ID pulse (color discrimination pulse) input pin (CMOS level VIH = 2.5V) ID = L C0 CR C1 CB
41
ID
41
40A
ID = H C0 CB C1 CR
1k
100k
1.8 to 5V (Control) 42 B MTX 0V (Preset)
15k 15k 147 100k
B signal operations MTX coefficient adjustment pin (Coefficient 0.22) Refer to Note 2.
80A
42
43
CLP C MPX2
2.7 to 3.1V
1k 147 43 44
147 6k 6k
Capacitor connecting pin for MPX clamp (Clamp at CLP2)
44
CLP C MPX1
2.7 to 3.1V
40A
- 10 -
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
100k
1.8 to 5V (Control) 45 R MTX 0V (Preset)
30k 300k 147 100k
R signal operations MTX coefficient adjustment pin (Coefficient 0.617) Refer to Note 2.
40A
45
48
DLC1 IN
C-Couple input 3.1 to 3.5V C-Couple input 3.6 to 4.0V C-Couple input 3.6 to 4.0V
2.6k
2.6k
1k
DL C1 signal input pin Sig: Typ. 150mVp-p (Negative polarity) DL Y1 signal input pin Sig: Typ. 150mVp-p (Negative polarity)
1k
147
55
DLY1 IN
48 55 56
56
DLY2 IN
150A
11A
DL Y2 signal input pin Sig: Typ. 150mVp-p (Negative polarity)
S2 signal input pin
147 147 50 7.5k 40A 40A
49
S2 IN
1.9V
49
Sig: Typ. 500mV Max. 1500mV
S1 signal input pin 50 S1 IN 1.9V
40A 40A 40A 40A 40A
Sig: Typ. 500mV Max. 1500mV
- 11 -
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
1k 147 1k
2.6k
51
CLP C Y0
3.3 to 3.7V
51 40A 150A
Capacitor connecting pin for Y0 clamp (Clamp at CLP4)
1k
1.8 to 5V (3H Mode) 57 Y2 GAIN 0V (2H Mode)
147 57
15k
DL Y2 signal gain control pin (1H delay line gain compensation) V-APCON mode selection 0V: 2H Mode 1.8 to 5V: 3H Mode
80A
58
GND2
GND Connecting pin of the external resistor that determines the characteristics of the LPF for 1H DL. (External resistor in the range of 15 to 27k) Connecting pin of the external resistor that determines the characteristics of the chroma LPF (LPF for R, G, B, CS). (External resistor in the range of 15 to 62k)
59
LPF Adj. 1
1.8 to 2.2V
5k
20k
300
60
LPF Adj. 2
1.8 to 2.2V
10A 59 60
- 12 -
CXA1391Q/R
PIn No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
300
300
61
LPF Adj. 3
1.8 to 2.2V
10A
Connecting pin of the external resistor that determines the characteristics of the LPF for V-APCN. (External resistor in the range of 15 to 62k) When connected to Vcc, the LPF for V-APCN turns OFF.
120k
61
62
Vcc
Power supply 5V (Typ.)
1k
100k
0V
(Typ. curve)
63
Y- CONT 1.8 to 5V (Control)
30k 30k 147
YH curve adjustment
40A
63
10k
YH signal input 64 YH IN 0.95V Sig: Typ. 220mV Max. 660mV
64
- 13 -
CXA1391Q/R
Electrical Characteristics Item Current consumption S2-S1 Amp Gain Symbol ID SSG Input: S1 IN = -62.5mV, S2 IN = 62.5mV Calculations: DLC0 OUT/S1 IN Conditions Min. 25 -3 Typ. 34.5 -1.95 Max. 43 -1 Unit mA dB
DLC1 gain control
Max.
Input: DLC1IN = 100mV Conditions: C1Gain = 5V DLC1H C-level = 5V Calculations: (WB-R/DLC1IN) -CG Note2) DLC1L SAG Conditions: C1Gain = 0V (Others same as DLC1H) Input: S1 IN = 500mV Calculations: DLY0OUT/S1 IN Input: S1 IN = S2 IN = 300mV Conditions: C-level = 5V Calculations: WB-G (ID = H, L average) Input: S1 IN = S2 IN = 62.5mV Conditions: C-level = 5V Calculations: WB-G/GY (ID = L) ID = H (Others same as GCR) Input: S1 IN = -62.5mV, S2 IN = 62.5mV Conditions: C-level = 5V Calculations: WB-R (ID = L) Input: S1 IN = S2 IN = 500mV Conditions: C-level = 5V Calculations: WB-R/RCR (ID = H) RMTX = 5V (Others same as RYP) RMTX = 1.8V (Others same as RYP) Input: S1 IN = 62.5mV, S2 IN = -62.5mV Conditions: C-level = 5V Calculations: WB-B (ID = H) Input: S1 IN = S2 IN = 500mV Conditions: C-level = 5V Calculations: WB-B/BCB (ID = H) BMTX = 5V (Others same as BYP) BMTX =1.8V (Others same as BYP)
6
7
9
dB
Min. S1+S2 Amp
-2 -15
-0.85 -14
0 -13
dB dB
Gch Y Chroma matrix (Gch) Note 3) CR/Y -CB/Y Rch CR Chroma matrix (Rch) Note 3)
GY
80
100
120
mV
GCR GCB RCR
0.9 -1.1 70
1 -1 85
1.1 -0.9 100
-- -- mV
Y (Preset) Y (Max.) Y (Min.) Bch-CB
RYP RYH RYL BCB
0.15 0.22 0.11 80
0.168 0.186 0.25 0.125 100 0.27 0.14 120
-- -- -- mV
Chroma matrix (Bch) Note 3)
Y (Preset) Y (Max.) Y (Min.)
BYP BYH BYL
0.2 0.31 0.13
0.22 0.34 0.15
0.24 0.37 0.17
-- -- --
- 14 -
CXA1391Q/R
Item
Symbol
Conditions Input: DLC1IN = -200mV Conditions: C-level = 5V RCONT = 4.6V (ID = H) Calculations: WB-R/WB-RTyp. Note 4) WB-R Typ. is the tested output of WB-R when RCONT is set to 4V (Other inputs, conditions same as RCH) Test: RCONT = 2.5V (Others same as RCH) Input: DLC1IN = 150mV Conditions: C-level = 5V BCONT = 4.6V (ID = L) Calculations: WB-B/WB-BTyp. Note 4) WB-B Typ. is the tested output of WB-B when BCONT is set to 4V (Other inputs, conditions same as BCH) Test: BCONT = 2.5V (Others same as BCH) Input: DLC1IN = -200mV Conditions: RCONT = 2.5V RGAIN = 5V C-level = 5V (ID = H) Calculations: WB-R/WB-RMin. WB-R Min. is the tested WB-R, when tested under the same conditions as RCL. Input: DLC1IN = 150mV Conditions: BCONT = 2.5V BGAIN = 5V C-level = 5V (ID = L) Calculations: WB-B/WB-BMin. WB-B Min. is the tested WB-B, when tested under the same conditions as BCL.
Min.
Typ.
Max.
Unit
RCONT Max.
RCH
7.5
8.2
8.5
dB
RCONT Min.
RCL
-8.4
-7.9
-7.4
dB
BCONT Max. WB GAIN BCONT Min.
BCH
7.5
8.2
8.5
dB
BCL
-8.4
-7.9
-7.4
dB
RGAIN Max.
RGH
8.6
9.2
--
dB
BGAIN Max.
BGH
11.4
12.2
--
dB
- 15 -
CXA1391Q/R
Item
Symbol
Conditions Input: S1IN = 200mV S2IN = 160mV DLC1IN = 220mV Conditions: C- CONT = WB DC = C-Slice = C-level = 5V RCONT = 2.5V BCONT = 4.6V (ID = L) Calculations: B-Y OUT/WB-B Conditions: R-Y GAIN = 1.8V Calculations: R-Y OUT/WB-B (Others same as BMBY) Conditions: BCONT = 4V 1. B-Y OUT is tested when B-Y gain = 0V and taken as A. (Other conditions are the same as BMBY) 2. B-Y OUT is tested when B-Y gain = 5V and taken as B. (Other conditions are the same as BMBY) Calculations: B/A
Min.
Typ.
Max.
Unit
R-G OUT/ WB-B
BMBY
0.4
0.44
0.48
--
R-Y OUT/ WB-B Bch color difference matrix Note 5)
BMRY
-0.24 -0.21 -0.17
--
B-Y GAIN Max.
BMG
3.0
3.3
--
--
B-Y Hue Max.
BMHH
Conditions: B-Y HUE = 1.8V (Others same as BMBY) Calculations: R-Y OUT/B-Y Typ. 0.58 B-Y Typ. is the value of the tested B-Y OUT when B-Y hue=0V (Other conditions are the same as BMBY). Note 6) B-Y HUE = 5V (Others same as BMHH) Input: S1IN = 830mV S2IN = 660mV DLC1IN = -230mV Conditions: WB-DC = C-level = 5V RCONT = BCONT = 2.5V 1. R-Y OUT is tested when R-Y gain = 0V and taken as A. 2. R-Y OUT is tested when R-Y gain = 1.8V and taken as B. Calculations: B/A Input: (The same as GMR) Conditions: 1. B-Y OUT is tested when B-Y gain = 0V and taken as A. 2. B-Y OUT is tested when R-Y gain = 1.8V and taken as B. (Others same as GMR) Calculations: B/A --
0.68
--
--
B-Y Hue Min.
BMHL
-0.67 -0.58
--
R-Y/R-G Gch color difference matrix Note 5) B-Y/B-G
GMR
0.81
0.85
0.89
--
GMB
0.63
0.66
0.7
--
- 16 -
CXA1391Q/R
Item
Symbol
Conditions Input: DLY1IN = -400mV Conditions: C-level = 5V Y1GAIN = 1.8V C-Slice = 1.8V (ID = H) Calculations: C-Slice Typ. -TP C-Slice Typ. is the TP output of C-Slice = 0V. Conditions: C-Slice =5V (Others same as CSLL) Input: DLY1IN = -200mV S1IN = S2IN = 500mV Conditions: Y1GAIN = 1.8V C-level is valied and adjusted to obtain 400mV at WB-G. After that C-level is fixed during test. WB-DC is set to OPEN during C-level adjusted and set to 5V during test. Calculations: WB-G is tested. Input: DLY1IN = -400mV S1IN = S2IN = 1000mV Conditions: Same as Typ. Calculations: WB-G/ Typ. Input: DLY1IN = -50mV S1IN = S2IN = 125mV (Others same as L8) Input: DLY1IN = -200mV S1IN = S2IN = 500mV Conditions: C CONT = 1.8V Calculations: WB-G/ Typ. Input: DLY1IN = -400mV S1IN = S2IN = 1000mV (Others same as M4) Input: DLY1IN = -50mV S1IN = S2IN = 125mV (Others same as M4) Input: DLY1IN = -200mV S1IN = S2IN = 500mV Conditions: C CONT = 1.8V Calculations: WB-G/ Typ. Input: DLY1IN = -400mV S1IN = S2IN = 1000mV (Others same as H4) Input: DLY1IN = -50mV S1IN = S2IN = 125mV (Others same as H4)
Min.
Typ.
Max.
Unit
Typ.-Min. C-Slice
CSLL
0
5
15
mV
Typ.-Max.
CSLH
95
120
145
mV
C- CONT=0V Typ. Gch-WB=400mV
450
500
550
mV
C- CONT=0V L8 Gch-WB=800mV
1.13
1.2
1.25
--
C- CONT=0V L1 Gch-WB=100mV Gch curve
0.36
0.4
0.44
--
C- CONT=1.8V M4 Gch-WB=400mV
0.9
1
1.1
--
C- CONT=1.8V M8 Gch-WB=800mV C- CONT=1.8V M1 Gch-WB=100mV
1.13
1.2
1.25
--
0.45
0.5
0.55
--
C- CONT=5V H4 Gch-WB=400mV
0.9
1
1.1
--
C- CONT=5V H8 Gch-WB=800mV C- CONT=5V H1 Gch-WB=100mV
1.13
1.2
1.25
--
0.26
0.3
0.35
--
- 17 -
CXA1391Q/R
Item Y1.0 (Typ.) Y2.0/Y1.0 Y0.5/Y1.0 Y Y0.5 (Max.)/ Y1.0 Y0.5 (Min.)/ Y1.0
Symbol YT Y2.0 Y0.5
Conditions Input: YHIN = 220mV Calculations: DLYHOUT Input: YHIN = 440mV Calculations: DLYHOUT/YT Input: YHIN = 110mV Calculations: DLYHOUT/YT Input: YHIN = 110mV Conditions: Y CONT = 1.8V Calculations: DLYHOUT/YT Input: YHIN = 110mV Conditions: Y CONT = 5V Calculations: DLYHOUT/YT Input: YHIN = 220mV Conditions: DLYHGAIN = 1.8V Calculations: TP/DLYHOUT Input: DLYHIN = YT x 0.7 Conditions: Same as TPY Calculations: TP/-DLYHOUT Input: S1IN = S2IN = 500mV DLY1IN = 200mV Conditions: Y1GAIN = 1.8V Calculations: TP/WB-G Input: YHIN = 220mV DLYHIN = - [YT x -3.5dB] Conditions: DLYHGAIN = 1.8V Calculations: TP is tested to check that the signal level is below 0mV in relation to black level. Note 8) Input: YHIN = 220mV DLYHIN = - [YT x -12dB] Conditions: DLYHGAIN = 5V Calculations: TPTP is tested to check that the signal level is over 0mV in relation to black level. Note 8) Input: DLC1IN = 200mV Conditions: 1. WB-G is tested when C-level = 5V and taken as GC-level Min. 2. WB-G is tested when C-level = 1.8V and taken as GC-level Max. (Both 1 and 2 test at ID-H.) Calculations: GC-level Max. / GC-level Min.
Min. -440 1.23 0.59
Typ. -400 1.37 0.66
Max. -360 1.51 0.73
Unit mV -- --
YH
0.64
0.71
0.78
--
YL
0.54
0.6
0.66
--
TP (YH)
TPY
-5
-4
-3
dB
TP
TP (DLYH)
TPDY
-5 Note 7)
-4
-3
dB
TP (GWBS)
TPG
-2
0
2
dB
Min. Gain
YLG
--
--
3.5
dB
YH AMP
Max. Gain
YHG
12
--
--
dB
Chroma level Max./Min.
GCL
1.55
1.65
1.75
--
WB DC
WDDC Test: WB-DC
1.4
1.6
2
V
- 18 -
CXA1391Q/R
Item
Symbol
Conditions Input: S1IN = 150mV S2IN = 450mV Conditions: C- CONT = WB DC = C-Slice = C-level = 5V RCONT = 4.6V BCONT = 2.5V BGAIN = 1.8V (ID = L) Calculations: YLOUT/WB-R Input: S1IN = 200mV S2IN = 160mV DLC1IN = 220mV Conditions: C- CONT = WB DC = C-Slice = C-level = 5V RCONT = 2.5V BCONT = 4.6V (ID = L) Calculations: YLOUT/WB-B Input: S1IN = 830mV S2IN = 660mV DLC1IN = -230mV Conditions: WB-DC = C-level = 5V RCONT = BCONT = 2.5V Calculations: YLOUT/WB-G Input: YHIN = 220mV Calculations: YHOUT1 is tested. Input: DLYHIN = - (YT x -4dB) Conditions: DLYHGAIN = 1.8V Calculations: YHOUT1/YH1Z Note 8) Input: YHIN = 220mV Calculations: YHOUT2/YH1Z Input: YHIN = 220mV Conditions: DLYHGAIN = 1.8V Calculations: YHOUT2/YHOUT2Typ. YHOUT2Typ. is YHOUT2 output tested at YH2Z. Input: S1IN = S2IN = 125mV Conditions: VAP GAIN = 1.8V VAP Slice = 1.8V Y2 GAIN = 1.8V Calculations: VAP OUT is tested. Input: S1IN = S2IN = 1000mV Conditions: Y2 GAIN = 1.8V 1. VAP OUT is tested when VAP Slice=1.8V and taken as SMin. 2. VAP OUT is tested when VAP Slice=5V and taken as SMax. Calculations: SMax.-SMin. Note 10)
Min.
Typ.
Max.
Unit
YLOUT/ ROUT
YLR
0.27
0.3
0.34
--
YL Note 5) YLOUT/ BOUT
YLB
0.08
0.1
0.12
--
YLOUT/ GOUT
YLG
0.54
0.6
0.66
--
YHOUT1 (OH mode)
YH1Z
900
1000
1100
mV
YHOUT1 1H/0H
YH1O
-1
0
1
dB
YHOUT2 (0H) /YHOUT1
YH2Z
-1
0
1
dB
YHOUT2 (1H) /YHOUT1
YH2O
-6.5
-6
-5.5
dB
VAP Typ. VAPT Note 9)
-250
-200
-150
mV
VAP Slice VS Note 9)
256
320
384
mV
- 19 -
CXA1391Q/R
Item
Symbol
Conditions Input: S1IN = S2IN = 500mV DLY1IN = -200mV Conditions: VAP GAIN = VAP Slice = Y1GAIN = 1.8V Calculations: VAP-OUT is tested to check that the signal level is over 0mV in relation to black level. Input: S1IN = S2IN = 500mV DLY1IN = -110mV Conditions: VAP GAIN = VAP Slice = 1.8V Y1GAIN = 5V Calculations: VAP-OUT is tested to check that the signal level is below 0mV in relation to black level. Input: S1IN = S2IN = -167mV DLY2IN = -66.7mV Conditions: VAP GAIN = VAP Slice = Y1GAIN = Y2GAIN = 1.8V Calculations: VAP-OUT is tested to check that the signal level is over 0mV in relation to black level. Input: S1IN = S2IN = -167mV DLY2IN = -37.5mV Conditions: Y2GAIN = 5V (Others same as DY2L) Calculations: VAP-OUT is tested to check that the signal level is below 0mV in relation to black level. Input: S1IN = S2IN = 167mV Conditions: Y1GAIN = Y2GAIN = 1.8V CS GAIN = 5V Calculations: CS OUT is tested. Conditions: CS GAIN = 0V (Others same as VCST) Calculations: CS OUT/VCST Conditions: CS GAIN = 1.8V (Others same as VCSL) Input: CS-IN = 500mV
Min.
Typ.
Max.
Unit
Min. DLY1 gain Note 11) Max.
DY1L
--
--
0
dB
DY1H
5
--
--
dB
Min. DLY2 gain Note 11)
DY2L
--
--
0
dB
Max.
DY2H
5
--
--
dB
VCS Typ.
VCST
90
120
150
mV
CS VCS Min. Note 12) VCS Max. VCS Typ. VCSH CST VCSL
--
0
0.05
--
4.4 440 465
-- 490
-- mV
- 20 -
CXA1391Q/R
Note 1) For pins without specific instructions regarding input, feed the DC value shown on the Test Circuit. Calculations are mentioned utilizing the pin name or the electrical characteristics symbols. Otherwise, for exceptional notations explanatory notes, are given with every case. Note 2) In this item, the gain of DLC1 amplifier exclusively is calculated. CG is the gain of the system from DLC1 IN to WB-R from which DLC1 GC amplifier gain has been excluded. --CG calculating method-- In the actual calculation, the system on C0 side is utilized. Input: S1IN = -62.5mV S2IN = 62.5mV Condition: Same as DLC1H Calculations: CG = 20log (WB-R/DLC0OUT) Note 3) Chroma matrix operations R = 2 [CR + Y] G = Y - (CR + CB) B = 2 [CB + (Y - C)]
: Control with RMTX (Preset 0.167) : Control with BMTX (Preset 0.22)
Note 4) With the typical gain taken when R CONT is at 4V, compare with the gain during Max. and Min. The same for B CONT. Note 5) Adjustment and testing is performed so that signals are output only for each of R, G, B channels respectively. Note 6) Comparison with B-Y OUT when R-Y HUE = 0V (HUE OFF). The same for B-Y HUE. Note 7) The compensation of difference in gain of YH0 andYH1 is as follows. 1) At DLYH GAIN = 1.8V, DLYH amplifier gain is 3dB. 2) Test DLYH OUT (tested at YrT) when YH IN = 220mV signal is input. 3) The difference in gain between YH0 and YH1 is compensated by inputting the signal as -3dB to DLYH IN. Note 8) The amplifier input is varied and the gain confirmed. Note 9) VAP (Vertical Aperture Compensation) Note 10) Dark slice variable volume. (Output level difference between the value slice volume at Max. and slice volume at Min.) Note 11) Utilizing V-APCN 2H mode, DLY1 amplifier exclusive gain is obtained through operations. However, as the amplifier gain cannot be tested directly, only the upper and lower limits of the gain control are checked according to the following method. (a) Lower limit check S1 IN = S2 IN = 500mV (At that time KNEE circuit input turns to 200mV) DLY1 IN = -200mV (For others refer to the conditions chart) In this condition, if we have VAP OUT 0, this indicates that DLY1 amplifier is below 0dB. (b) Upper limit check S1 IN = S2 IN = 500mV DLY1 IN = -110mV (in (a) the -5dB of -200mV) In this condition, if we have VAP OUT 0, this indicates that DLY1 amplifier is above 5dB. Note 12) CS (Chroma Suppress) - 21 -
CXA1391Q/R
Timing Chart for Testing
Input waveform
Differs with each test DLYH IN CS IN DLC1 IN S1 S2 DLY1 IN DLY2 IN YH IN
30
30
30
30
5V tD 0V
5V CLP2 0V 5
2
2
5
5V CLP4 0V 15
2
2
15
Output waveform
Output signal
DLYH OUT YH OUT1 YH OUT2 TP VAP_OUT
B - Y OUT R - Y OUT CS OUT YL OUT WB_R
WB_G WB_B DLC0 OUT DLY0 OUT DLY1 OUT
- 22 -
Test Circuit (Typ. setting)
0V 0.1 0V 0.1 V 0.1 V 0V ID 0V 4V 4V 0V 0.1V 0.1V 0.1V 0V
DLC1 IN
C1 GAIN
DLCO OUT
R MTX
CLP C MPX1
CLP C MPX2
B MTX
ID
B GAIN
B CONT
R CONT
R GAIN
CLP C B
48 47 34 44 42 41 39 33 36
46 45 43 38
40
37
S2 IN
49 32
C0 LPF C SLICE 0V V 5V V WB DC WB B WB G WB R C-r CONT
27
WB CONTROL
DC 1.9V
50
S1 IN Y0 GC
30
DC 1.9V CLP (CLP4) LPF
31
CLP C G
35
CLP C YO
C0 CLP -CB B LPF (CLP2) CR G MATRIX WB AMP & Y C1 MPX R LPF CLP (CLP2)
DLY0 OUT
52 29
LPF
Y0 LPF
DLY1 OUT
53 28
SLICE
R-r
Y1 GAIN
54
G-r
Y0 Y1
R-WB G-WB B-WB B-r
0.1
CLP (CLP4)
51
CLF C R
C LEVEL
0V
55
0V
26
DLY1 IN GC CLP (CLP4) Y2 CLP (CLP4) Y1 LPF
Y2 Y1
Y0
0.1 Y2 GAIN
KNEE
KNEE
KNEE
CLP V-APCN (CLP4)
5V
62
10 YH1 CLP (CLP4) GC YH1
VCC
YH0
CS-Y CLP (CLP4)
B-Y R-Y MTX R-Y B-Y Hue & GC
5V 62k
61
V-APCN
G ch SLICE SLICE CLP
DC 0.95V
64 1 2 3 4 5 6 7
CLP (CLP2) r
YH0
GC
TP
CLP4
CLP2
DLYH IN
YH OUT 1
YH OUT 2
VAP OUT
CLP C YH
DLYH OUT
DLYH GAIN
DC 3.65V CLP C DLYH
Note 1) F is unit of capacitor Note 2) indicates testing pin. (AC, DC test) Note 3) Input pin DC value indicates input signal black level. Note 4) indicate relay, side, normal close.
0.1 0.1
CXA1391Q/R
0V
CLP2
0V
CLP C VAP
0.1
VAP SLICE
CLP4
VAP GAIN
0V
CLP C CS
0.1
CS IN
- 23 -
56
0V
57
ABS CS-Y CS LPF
GC
CS VAP MAX
YL MTX
GC
LPF
R-r G-r B-r
0.1 DLY2 IN
r
GND 1 YL OUT
25
CS OUT
24
GND 2
58
- - 2H APCN 3H APCN
-
23
CS GAIN R-Y HUE
22
0V 0V B-Y HUE
21
27k
59
LPF ADJ 1
62k
60
LPF ADJ 2 LPF
V-APCN
0V R-Y OUT
20
62k
LPF ADJ 3
B-Y OUT
19
Y-r CONT
63
0V
B-Y GAIN
18
0V R-Y GAIN
17
YH IN
0V
8 9 10 11 12 13 14 15 16
0.1
CXA1391Q/R
Standard Control Characteristics (Vcc = 5V, Ta = 25C)
C1 GAIN control characteristics
3 GAIN converted into unit 0.3
R-MTX coefficient
2
GAIN
0.2 1 Preset
2
3 C1 GAIN voltage (V)
4
5
0.1
0
2
3 R-MTX voltage (V)
4
5
B-MTX coefficient
0.4 7
R GAIN control characteristics
6
0.3
5
Preset 0.2
GAIN
4 3 0.1 0 2 3 4 5 2 0 2 3 4 5 R GAIN voltage (V) B-MTX voltage (V)
B GAIN control characteristics
10 3
R/B CONT control characteristics
8 2 6
1/GAIN
1 2
GAIN
4
2 2 3 4 5 3 4 5 B GAIN voltage (V) R/B CONT voltage (V)
- 24 -
CXA1391Q/R
C-SLICE control characteristics
1.5 150
C-SLICE control characteristics
BLACK DC difference between sliced signal and during sliced OFF
100
GAIN
1
(mV)
50 0 2 3 C-LEVEL voltage (V) 4 5 2 3 4 5 C-SLICE power supply (V)
0.5
R-Y/B-Y GAIN control characteristics
3
R-Y/B-Y HUE control characteristics
40 30 20
2 10
GAIN
0 -10 -20 -30
1
2
3
4
5
2
3
4
5
R-Y/B-Y GAIN voltage (V)
R-Y/B-Y HUE voltage (V)
Y1/Y2 GAIN control characteristics
3 400
CS GAIN control characteristics
CS output during S1 = S2 = 125mV input (3H_Mode) 2 300
GAIN
(mV)
1 2 3 4 5
200
100
2
3
4
5
Y1/Y2 GAIN voltage (V)
CS GAIN voltage (V)
- 25 -
CXA1391Q/R
DLYH GAIN control characteristics
15 400
VAP control characteristics
VAP_OUT output during S1 = S2 = 250mV input (3H_Mode)
VAP OUT (mV)
2 3 4 DLYH GAIN voltage (V) 5
10
300
GAIN (dB)
200
5
100
0
0 2 3 4 VAP GAIN voltage (V) 5
VAP SLICE control characteristics
300
(mV)
200
100 VAP GAIN = 0V Diminution of VAP OUT output level 2 3 4 VAP SLICE voltage (V) 5
- 26 -
CXA1391Q/R
Standard Design Data
Chroma curve (standardize)
1.2
1.0
output (standardize)
0.8
0.6 1 0.4 2 3 Standardize at typical input (400mV) 1: C - CONT=1.6V (Max.) 2: C - CONT=0V (Typ.) 1: C - CONT=5V (Min.) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 input (standardize) 1.6 1.8 2.0 2.2
0.2
YH curve (standardize) (mV)
1.4 1.2
output (standardize)
1.0 0.8 0.6 12 0.4 0.2 3 Standardize at typical input (220mV) 1: Y - CONT=1.6V (Max.) 2: Y - CONT=0V (Typ.) 1: Y - CONT=5V (Min.) 0.6 0.8 1.0 1.2 1.4 1.6 input (standardize) 1.8 2.0 2.2
0.2
0.4
V-APCN Knee (standardize) (mV)
1.0
Knee output (standardize)
0.8
0.6
0.4
0.2 Standardize at typical input (S1 = S2 = 500mV) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Knee input (standardize)
- 27 -
CXA1391Q/R
Pre-Filter Adjust characteristics
300
DL Y0 out S1, S2 DL C0 out (fc: -3dB)
3.0
250
2.5
D (nsec)
fc (MHz)
15k 20k 25k 30k
200
2.0
150
1.5
100 10k
1.0 10k 15k 20k 25k 30k REXT [LPF ADJ1 (59PIN) ] () REXT [LPF ADJ1 (59PIN) ] ()
Chroma Adjust characteristics
800
S1, S2
R-Y out B-Y out
600
D (nsec)
400 200 10k
20k
30k
40k
50k
60k
70k
80k
REXT [LPF ADJ2 (60PIN) ] ()
(fc: -3dB)
1.5
fc (MHz)
1.0
0.5 10k 20k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ2 (60PIN) ] ()
- 28 -
CXA1391Q/R
CS-VAP Adjust characteristics (S1, S2 CS OUT)
800
600
D (nsec)
400
10k
20k
30k
40k
50k
60k
70k
80k
REXT [LPF ADJ2 (60 PIN) ] ()
(fc: -3dB)
1.5
fc (MHz)
1.0
0.5 10k 20k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ2 (60 PIN) ] ()
- 29 -
CXA1391Q/R
CS-Y LPF Adjust characteristics (CS IN CS OUT)
600
400
D (nsec)
200
10k
20k
30k
40k
50k
60k
70k
80k
REXT [LPF ADJ2 (60 PIN) ] ()
(fc: -3dB)
2.0
1.5
fc (MHz)
1.0 0.5 10k 20k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ2 (60 PIN) ] ()
VAP LPF Adjust characteristics
- 30 -
CXA1391Q/R
VAP LPF Adjust characteristics (S1, S2 VAP OUT)
600
400
D (nsec)
200 10k
20k
30k
40k
50k
60k
70k
80k
REXT [LPF ADJ3 (61 PIN) ] ()
(fc: -3dB)
1.5
1.0
fc (MHz)
0.5 10k 20k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ3 (61 PIN) ] ()
- 31 -
CXA Series System Diagram
W/B CONTROLLER IHDL IHDL IHDL
CCD
DL
DETECTOR
51 47 41 34 39 33 36 34 33 31 30 35 32 29
50 44
49 48 45 43 42
46
40
38 37
36 35
YOCLP S1-IN
S2-IN
R-MIX
B-CLP
G-CLP
B-GAIN
B-CONT
DLC1-IN
C1-GAIN
R-CONT
R-GAIN
C LEVEL
CLP4
XSHD
XSHP
DLD
DLCO-OUT
MPX2-CLP
MPX1-CLP
OPIN-N
OPIN-P
SETUP
OP-OUT
AGC-SEL
AGC-OUT
AGC-CLP DETLEVEL
AGC-MAX
SHP-CLP1
AGC-CONT
39 VCC1 56 DLY2-IN
IRIS-GC 22 WB-R 28
40 YH-IN 41 YL-YH CLP 42 YL-YH IN 43 AGND 44 CLP4 45 CLP2 46 B-LEVEL 47 B-Y IN
55 DLY1-IN
WB-G 29
39 YH-CLP
FADER-MODE
SYNC-LEVEL
5V
38 DATA-IN
38 NOISE-SLICE
FADER-SIG
DET- 24 OUT VCC2 23
37 YTBLK 54 Y1-GAIN
WB-B 30
SHP-CLP2
SHP-OUT
Y-LEVEL
37 PG-IN
5V
OUT 53 DLY1-OUT
C- 32 SLICE WB-DC 31
SHPLEVEL DLE
SYNC
52 DLY0-
B-MTX
R-CLP
36
35
34
33
32
31 30
29
28
27
26
ID
25
28
27
26
25
WC 24
SETUP- 23 CLP V-OUT 22 VIDEO-OUT 21 CHROMA-OUT 20 CXA1392 Q/R DGND 19 C-IN 18 AVCC 17 C-OUT 16 CS-Y 15 CS-AGC 14 4FSC LALT BPF 5V
Y Vid C
40 XSP3 57 Y2-GAIN
IRIS-LEVEL 21 CGAM-CONT 27 CXA1391 Q/R GND 26 YL-OUT 25 CS-OUT 24 VCS-GAIN 23 R-Y HUE 22 B-Y HUE 21 R-Y 20 OUT
41 XSP2 58 GND 59 60 LPF-ADJ2
DET-CLP 20
42 XSP1
CXA1390 Q/R LPF-ADJ1
GND 19
43 GND
IRIS-CLP 18
44 FSHI
IRIS-OUT 17 5V
62 VCC 63 YGAM61 LPF-ADJ3
45 F3-CLP
VG-OUT 16
46 F2-CLP
WND 15 CONT YH-OUT1 YH-OUT2 TP CLP4 CLP2 VAP-OUT VAP-CLP CS-CLP CS-IN R-Y GAIN B-Y GAIN B-Y OUT
47 F1-CLP 64
PBLK 14 YH-IN
1 2 3 7 11 16 4 8 10 14 17 15 5 12 6 9 13 18 19
NC
NC
FSC-OUT
48 B-Y
BFG
BF
R-Y IN
R-Y CLP
YHCLP DLYH-IN
DLYH-CLP
DLYH-OUT
DLYH-GAIN
VAP-GAIN
XSH1
DC-OUT
GY-OUT
F1-OUT
F2-OUT
F3-OUT
CS-CLP
CS-CCD-SL
CS-CCD-GC
CS-OUT
CS-AGC-GC
1
2
3
4
5
6
CS-AGCSL
VAP-SLICE
DVCC
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
5V
5V
LPF DL LPF IHDL
LPF DL
12 11 10 9 8 7 6 5 4 3 2 1
CLP4
DB-IN
DR-IN
GND
CB-IN
CG-IN
XSH1 XSH2
CLP1
ID PBLK
YG-IN
YR-IN
YB-IN
YT-GC
DR-OUT
CT-BLK DB-OUT
DY-OUT
YT-BLK
DY-CLP
DY-IN
XSP1
XSP2 WND CR CG CB LPF SG CONTROLLER FOR TITLER YR YG YB 4fSC
13
14
15
16
17 18
19
VCC
20 21
22 23
24
TG
HD.VD CL
CLP4
XSHD
XSHP
BLK BF SYNC LALT
CXA1391Q/R
BFG
CT-GC
CLP2
HYSCONT TH-CONT COMP-IN COMPOUT
CXA1393AN/AM
CR-IN
CBLK CTBLK CLP
- 32 -
48 XSH2
CLP1 13
MODE 13
12
CXA1391Q/R
Package Outline CXA1391Q
Unit: mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
19 + 0.35 2.75 - 0.15 0.12 M 0.8 0.2 EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
CXA1391R
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 0.08 16 + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 QFP064-P-1010-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY
0.3g
- 33 -
0.5 0.2
(11.0)
16.3

▲Up To Search▲

Price & Availability of CXA1391Q

	To Download CXA1391Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .